A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS

An eye-opening monitor (EOM) architecture that can capture a two-dimensional (2-D) map of the eye diagram of a high-speed data signal has been developed. Two single-quadrant phase rotators and one digital-to-analog converter (DAC) are used to generate rectangular masks with variable sizes and aspect ratios. Each mask is overlapped with the received eye diagram and the number of signal transitions inside the mask is recorded as error. The combination of rectangular masks with the same error creates error contours that overall provide a 2-D map of the eye. The authors have implemented a prototype circuit in 0.13-μm standard CMOS technology that operates up to 12.5 Gb/s at 1.2-V supply. The EOM maps the input eye to a 2-D error diagram with up to 68-dB mask error dynamic range. The left and right halves of the eyes are monitored separately to capture horizontally asymmetric eyes. The chip consumes 330 mW and operates reliably with supply voltages as low as 1 V at 10 Gb/s. The authors also present a detailed analysis that verifies if the measurements are in good agreement with the expected results

A 10Gb/s eye-opening monitor in 0.13μm CMOS

An eye-opening monitor circuit in 0.13 μm CMOS operates from 1 to 12.5Gbit/s at 1.2V supply. It maps the input eye to a 2D error diagram with 68dB mask error dynamic range. Left and right halt of the eye are monitored separately to capture asymmetric eyes. Tested input amplitude is from 50 to 400mV. The chip consumes 330mW and works at 10Gb/s with a supply voltage as low as 1V

A low-power receiver with switched-capacitor summation DFE

A low power receiver with a one tap DFE was fabricated in 90mm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition directly at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. At 10Gb/s data rate, the receiver consumes less than 6.0mW from a 1.0V supply

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally

Flexible silicon photonic transmitter with segmented modulator and 32 nm CMOS driver IC

ConferenciaWe present a novel silicon photonic transmitter including 90nm CMOS segmented modulator co-packaged with low power 32nm CMOS driver IC. Optical equalization is demonstrated for the first time with the multi-segment Mach-Zehnder modulator at 22Gb/s. OCIS codes: (130.4110) Modulator; (250.3140) Integrated optoelectronic circuits

Flexible transmitter employing Silicon-segmented Mach–zehnder modulator with 32-nm CMOS distributed driver

Artículo científicoWe propose a flexible optical transmitter for shortreach optical interconnects that includes a silicon photonic segmented Mach-Zehnder modulator (MZM) driven by a distributed six-channel 32nm SOI CMOS driver integrated circuit. Optical equalization is demonstrated to extend the bandwidth limitation of the transmitter with NRZ signaling at 25Gb/s. We also generate four-level pulse amplitude modulation (PAM-4) signaling using the same transmitter architecture. Transmission of 46Gb/s PAM-4 signal with bit error rate (BER) well below hard-decision forward error correction limit (BER=3.8×10-3) is experimentally demonstrated. Low driver power consumption of 130 mW at 46Gb/s PAM-4, corresponding to 2.8 pJ/bit power efficiency, is also achieved

Four-channel WDM transmitter with heterogeneously integrated III-V/Si photonics and low power 32 nm CMOS drivers

Artículo científicoWe experimentally demonstrate a novel four-channel wavelength division multiplexing transmitter operating at 1.3 μm wavelength employing heterogeneously integrated III-V/Si photonic circuit copackaged with low-power 32-nm SOI CMOS driver integrated circuits (ICs). Error-free operation (BER < 10−12 ) has been achieved across all four channels for back-to-back, 2 and 10 km single-mode fiber transmission at 25 Gb/s per each channel, targeting intra- and inter-datacenter interconnect applications. Power consumption as low as 19.2 mW for four CMOS driver ICs has been recorded, which yields 0.19 pJ/bit energy efficiency

A WDM 4x28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs

A four-channel WDM silicon photonic transmitter with integrated lasers and modulators driven by low-power 32nm CMOS drivers, is demonstrated to operate at a data rate of 4×28Gb/s with BER<10-12 and power consumption of 10.0pJ/bit.IEEE Communications Society,IEEE Photonics Society,The Optical Societ